0.10 μm Ion-Implanted GaAs MESFETs with Low Cost Production Process

We have successfully fabricated 0.1 μm gate GaAs MESFETs using a low cost process. The result was obtained from optical lithography, resist etching, and ion-implantation technologies based on Single Resist layer Dummy gate (SRD) process. The novel feature of the SRD process is forming a sub-quarter micron gate with conventional optical lithography. We have obtained a 0.18 μm gate using this process. Achieving a smaller gate length of 0.1um is very difficult with this process due to the pattern size shift of the sputtered SiO2 opening. In this study, we use a collimated sputtering technique in the SRD process to reduce the pattern size shift. As a result, the pattern size shift of the SiO2 opening decreases to 0.02 μm allowing a 0.1 μm gate length to be obtained by using conventional optical lithography. The high-speed performance of fT =81 GHz and an fmax of 142 GHz are achieved with the refined SRD process. a)